View LT4256_4435126.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lt4363 1 4363fa 100ms/div 4363 ta01b v in 20v/div v out 20v/div 80v input surge c tmr = 6.8f i load = 500ma 27v adjustable clamp 12v 12v the lt ? 4363 surge stopper protects loads from high voltage transients. it regulates the output during an overvoltage event, such as load dump in vehicles, by controlling the gate of an external n-channel mosfet. the output is limited to a safe value allowing the loads to continue functioning. the lt4363 also monitors the voltage drop between the sns and out pins to protect against overcurrent faults. an internal amplifier limits the voltage across the current sense resistor to 50mv. in either fault condition, a timer is started inversely proportional to mosfet stress. before the timer expires, the f lt pin pulls low to warn of an impend - ing power down. if the condition persists, the mosfet is turned off. the lt4363-1 remains off until reset whereas the lt4363-2 restarts after a cool down period. two precision comparators can monitor the input supply for overvoltage (ov) and undervoltage (uv) conditions. when the potential is below the uv threshold, the external mosfet is kept off. if the input supply voltage is above the ov threshold, the mosfet is not allowed to turn back on. back-to-back mosfets can be used in lieu of a schottky diode for reverse input protection, reducing voltage drop and power loss. a shutdown pin reduces the quiescent current to less than 7a during shutdown. typical application features description high voltage surge stopper with current limit 4a, 12v overvoltage output regulator with 150v surge protection overvoltage protector regulates output at 27v during transient applications n withstands surges over 80v with v cc clamp n wide operating voltage range: 4v to 80v n adjustable output clamp voltage n fast overcurrent limit: less than 5s n reverse input protection to C60v n adjustable uv/ov comparator thresholds n low 7a shutdown current n shutdown pin withstands C60v to 100v n adjustable fault timer n controls n-channel mosfet n less than 1% retry duty cycle during faults, lt4363-2 n available in 12-pin (4mm 3mm) dfn, 12-pin msop or 16-pin so packages n automotive/avionic surge protection n hot swap?/live insertion n high side switch for battery powered systems n intrinsic safety applications l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and no r sense , thinsot and hot swap are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 0.1f 10 10m fdb33n25 v in 12v 4363 ta01 lt4363-2 gnd tmr out gate sns uv shdn ov fault output clamp at 16v enout flt fb 1k smaj58a 22f 0.1f v cc dc/dc converter gnd shdn v cc 4.99k 127k 49.9k 57.6k
lt4363 2 4363fa absolute maximum ratings v cc , shdn , uv, ov ................................... C60v to 100v sns, out ................................................. C0.3v to 100v sns to out ................................................. C30v to 30v gate (note 3) .................................. C0.3v to sns + 10v enout, flt .............................................. C0.3v to 100v fb ............................................................. C0.3v to 5.5v tmr ...................................................................... 0.5ma (notes 1, 2) lt4363-1 lt4363-1 lt4363-1 12 11 10 9 8 7 13 gnd 1 2 3 4 5 6 tmr enout flt gnd uv gnd fb out sns gate v cc shdn top view de package 12-lead (4mm 3mm) plastic dfn t jmax = 125c, ja = 43c/w exposed pad (pin 13) is gnd, connection to pcb optional 1 2 3 4 5 6 fb out sns gate v cc shdn 12 11 10 9 8 7 tmr enout flt gnd uv gnd top view ms package 12-lead plastic msop t jmax = 125c, ja = 135c/w top view s package 16-lead plastic so 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 out sns nc gate nc v cc nc shdn fb tmr nc enout flt gnd uv gnd t jmax = 125c, ja = 80c/w lt4363-2 lt4363-2 lt4363-2 12 11 10 9 8 7 13 gnd 1 2 3 4 5 6 tmr enout flt gnd uv ov fb out sns gate v cc shdn top view de package 12-lead (4mm 3mm) plastic dfn t jmax = 125c, ja = 43c/w exposed pad (pin 13) is gnd, connection to pcb optional 1 2 3 4 5 6 fb out sns gate v cc shdn 12 11 10 9 8 7 tmr enout flt gnd uv ov top view ms package 12-lead plastic msop t jmax = 125c, ja = 135c/w top view s package 16-lead plastic so 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 out sns nc gate nc v cc nc shdn fb tmr nc enout flt gnd uv ov t jmax = 125c, ja = 80c/w pin configuration operating temperature range lt4363c .................................................. 0c to 70c lt4363i ................................................ C40c to 85c storage temperature range de12 .................................................. C65c to 125c ms, so .............................................. C65c to 150c lead temperature (soldering, 10 sec) ms, so ............................................................. 300c
lt4363 3 4363fa order information lead free finish tape and reel part marking* package description temperature range lt4363cde-1 #pbf lt4363cde-1 #trpbf 43631 12-lead (4mm 3mm) plastic dfn 0c to 70c lt4363ide-1 #pbf lt4363ide-1 #trpbf 43631 12-lead (4mm 3mm) plastic dfn C40c to 85c lt4363cde-2 #pbf lt4363cde-2 #trpbf 43632 12-lead (4mm 3mm) plastic dfn 0c to 70c lt4363ide-2 #pbf lt4363ide-2 #trpbf 43632 12-lead (4mm 3mm) plastic dfn C40c to 85c lt4363cms-1 #pbf lt4363cms-1 #trpbf 43631 12-lead plastic msop 0c to 70c lt4363ims-1 #pbf lt4363ims-1 #trpbf 43631 12-lead plastic msop C40c to 85c lt4363cms-2 #pbf lt4363cms-2 #trpbf 43632 12-lead plastic msop 0c to 70c lt4363ims-2 #pbf lt4363ims-2 #trpbf 43632 12-lead plastic msop C40c to 85c lt4363cs-1 #pbf lt4363cs-1 #trpbf lt4363s-1 16-lead plastic so 0c to 70c lt4363is-1 #pbf lt4363is-1 #trpbf lt4363s-1 16-lead plastic so C40c to 85c lt4363cs-2 #pbf lt4363cs-2 #trpbf lt4363s-2 16-lead plastic so 0c to 70c lt4363is-2 #pbf lt4363is-2 #trpbf lt4363s-2 16-lead plastic so C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 12v, unless otherwise noted. symbol parameter conditions min typ max units v cc operating voltage range lt4363c lt4363i l l 4 4.5 80 80 v v i cc v cc supply current shdn open, out = sns = 12v shdn = 0v, out = sns = 0v l l 0.7 7 1.2 20 40 ma a a i r reverse input current v cc = C60v, shdn , uv, ov open v cc = shdn = uv = ov = C60v l l C0.5 C3 C3 C10 ma ma v gate gate drive v gate = (gate C sns);v cc = out v cc = 4v; i gate = C0.5a, 0a 9v v cc 80v; i gate = C1a, 0a l l 4.5 10 13 16 v v i gate(up) gate pull-up current v cc = gate = out = 12v v cc = gate = out = 48v l l C10 C10 C20 C25 C35 C40 a a i gate(dn) gate pull-down current overvoltage: fb = 1.5v, gate = 12v, out = 5v overcurrent: v sns = 150mv, v gate = 10v, out = 0v shutdown/uv mode: shdn = 0v, gate = 10v uv = 1v, gate = 10v l l l l 75 50 50 200 150 100 1000 1000 ma ma a a v fb fb servo voltage gate = 12v; out = 8v l 1.25 1.275 1.3 v i fb fb input current v fb = 1.275v l 0.2 1 a v sns current limit sense voltage v sns = (sns C out) v cc = 12v, out = 3v to 12v v cc = 48v, out = 3v to 48v l l 43 45 50 52 58 59 mv mv current limit foldback v cc = 12v, out = 0v to 1v v cc = 48v, out = 0v to 1v l l 15 16 25 27 35 36 mv mv i sns sns input current out = sns = 3v to 80v out = sns = 0v l l 20 C10 30 C15 a a
lt4363 4 4363fa note 2: all currents into device pins are positive all current out of device pins are negative. all voltages are referenced to gnd unless otherwise specified. note 3: an internal clamp limits the gate pin to a minimum of 10v above the out pin. driving this pin to voltages beyond the clamp may damage the device. symbol parameter conditions min typ max units i tmr tmr pull-up current, overvoltage tmr = 1v, fb = 1.5v, v ds = 0.5v tmr = 1v, fb = 1.5v, v ds = 75v l l C1.7 C42 C4 C50 C6 C58 a a tmr pull-up current, ov warning tmr = 1.325v, fb = 1.5v, v ds = 0.5v l C3 C5 C7 a tmr pull-up current, overcurrent tmr = 1v, v sns = 100mv, v ds = 0.5v tmr = 1v, v sns = 100mv, v ds = 80v l l C5 C190 C9 C250 C13 C310 a a tmr pull-up current, cool down tmr = 3v, fb = 1.5v, v sns = 0v, v ds = 0v l C1 C2.3 C3.5 a tmr pin pull-down current, cool down v tmr = 3v, fb = 1.5v, v sns = 0v, v ds = 0v l 1 2 4 a v tmr(f) v tmr(g) v tmr(r) tmr fault threshold tmr gate off threshold tmr restart threshold tmr rising tmr rising tmr falling, lt4363-2 l l l 1.235 1.335 0.47 1.275 1.375 0.5 1.31 1.41 0.53 v v v v tmr early warning window v tmr(g) C v tmr(f) l 80 100 120 mv v tmr(h) tmr cool down high threshold v cc = 7v to 80v, tmr rising l 3.7 4.3 5 v v uv uv input threshold uv rising l 1.24 1.275 1.31 v v uv(hyst) uv input hysteresis 12 mv v ov ov input threshold ov rising l 1.24 1.275 1.31 v v ov(hyst) ov input hysteresis 7.5 mv i in uv, ov input current uv = 1.275v uv = C60v l l 0.2 C1 1 C2 a ma i leak f lt , enout leakage current f lt , enout = 80v l 0.5 2.5 a v ol f lt , enout output low i sink = 0.1ma i sink = 2ma l l 300 2 800 9 mv v v out(th) out high threshold v out = v cc C v out , enout from low to high l 0.25 0.5 0.75 v v out(rst) out reset threshold enout from high to low l 1.9 2.7 3.6 v i out out input current v cc = out = 12v, shdn open v cc = out = 12v, shdn = 0v l l 0.25 0.25 0.5 1 ma ma v shdn shdn threshold v cc = 4v to 80v l 0.6 0.4 1.4 1.7 2.1 v v v shdn(z) shdn open voltage v cc = 4v to 80v l 2.2 v i shdn shdn current shdn = 0.4v l C1 C4 C8 a t reset shdn reset time shdn 0.4v; lt4363-1 l 100 s d retry duty cycle; overvoltage v cc = 80v, out = 16v, fb = 1.5v; lt4363-2 l 1 2 % retry duty cycle; output short v cc = 12v, out = 0v, ?v sns = 100mv; lt4363-2 l 0.76 1 % t off(uv) undervoltage turn off propagation delay uv steps from 1.5v to 1v l 2 5 s t off(ov) overvoltage turn off propagation delay fb steps from 0v to 1.5v; out = 0v l 0.25 1 s t off(oc) overcurrent turn off propagation delay ?v sns steps from 0v to 150mv; out = 0v l 1 2.5 s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 12v, unless otherwise noted.
lt4363 5 4363fa specifications are at v cc = 12v, t a = 25c, unless otherwise noted. typical performance characteristics shdn current vs temperature gate pull-up current vs v cc gate pull-up current vs temperature gate pull-down current vs temperature: overcurrent gate pull-down current vs temperature: overvoltage gate drive voltage vs gate pull-down current v gate vs i gate supply current vs supply voltage (i cc vs v cc ) supply current during shutdown vs temperature (i cc(shdn) vs temperature) supply current during shutdown vs supply voltage (i cc(shdn) vs v cc ) v cc (v) 0 i cc (a) 1000 800 600 400 200 0 4363 g01 80706050 20 40 10 30 v cc (v) 0 i cc (a) 6 5 4 3 2 1 0 4363 g03 80706050 20 40 10 30 out = sns = 0v temperature (c) ?50 i cc (a) 8 7 5 6 4 2 3 1 0 0 50 ?25 25 100 4363 g02 125 75 out = sns = 0v temperature (c) ?50 i cc(shdn) (a) 3.0 2.5 1.5 2.0 0.5 1.0 0 0 50 ?25 25 100 4363 g04 125 75 shdn = 0v shdn = 0.4v v cc (v) 0 i gate(up) (a) 40 25 20 35 30 15 10 5 0 4363 g05 80706050 20 40 10 30 v cc = sns = out = gate temperature (c) ?50 0 50 ?25 25 100 125 75 i gate(up) (a) 40 25 20 35 30 15 10 5 0 4363 g06 v cc = sns = out temperature (c) ?50 0 50 ?25 25 100 125 75 i gate(dn,oc) (ma) 200 125 100 175 150 75 50 25 0 4363 g07 ?v sns = 150mv out = 0v gate = 10v temperature (c) ?50 0 50 ?25 25 100 125 75 i gate(dn,ov) (ma) 200 125 100 175 150 75 50 25 0 4363 g08 sns = out = 5v gate = 12v fb = 1.5v i gate (a) 0 ?v gate (v) 16 14 10 6 2 12 8 4 0 6 4363 g09 108 42 v cc = sns = out
lt4363 6 4363fa typical performance characteristics overvoltage tmr current vs (v cc C v out ) overcurrent tmr current vs (v cc C v out ) warning period tmr current vs v cc tmr pull-down current vs temperature tmr pull-up current (cool down) vs temperature output low voltage vs current gate drive at temperature (v gate vs temperature) gate drive vs supply voltage (v gate vs v cc ) tmr high threshold vs supply voltage specifications are at v cc = 12v, t a = 25c, unless otherwise noted. temperature (c) ?50 ?v gate (v) 14 13 11 12 10 0 50 ?25 25 100 4363 g10 125 75 v cc = sns = out i gate = ?1a i gate = 0a v cc (v) 0 ?v gate (v) 16 10 8 14 12 6 4 2 0 4363 g11 80706020 8 16 4 12 v cc = sns = out i gate = 0a i gate = 1a v cc (v) 0 v tmr (v) 5 4 3 2 1 4363 g12 80706050 20 40 10 30 v cc ? v out (v) 0 i tmr( u p,o v ) (a) 50 40 30 20 10 0 4363 g13 80706050 20 40 10 30 tmr = 1v v cc ? v out (v) 0 i tmr ( u p,o c ) (a) 260 220 160 120 80 40 0 4363 g14 80706050 20 40 10 30 tmr = 1v v cc (v) 0 i tmr (ov,ew ) (a) 2.5 2.0 1.5 1.0 0.5 0 4363 g15 80706050 20 40 10 30 ?v ds = 0.5v temperature (c) ?50 i tmr(dn) (a) 2.4 2.0 1.2 1.6 0.4 0.8 0 0 50 ?25 25 100 4363 g16 125 75 tmr = 1v temperature (c) ?50 i tmr (up,cool ) (a) 3.0 2.5 1.5 2.0 0.5 1.0 0 0 50 ?25 25 100 4363 g17 125 75 tmr = 3v i sink (ma) 0 v ol (v) 6 5 4 3 2 1 0 4363 g18 3.02.52.01.51.00.5 out = sns = 3v
lt4363 7 4363fa typical performance characteristics reverse current vs reverse voltage current limit at supply voltage (v sns vs v cc ) overvoltage turn-off time vs temperature overcurrent turn-off time vs temperature specifications are at v cc = 12v, t a = 25c, unless otherwise noted. temperature (c) ?50 0 50 ?25 25 100 125 75 t off(ov) (ns) 350 200 100 300 150 250 50 0 4363 g19 temperature (c) ?50 0 50 ?25 25 100 125 75 t off(oc) (s) 1.4 0.8 0.4 1.2 0.6 1.0 0.2 0 4363 g20 out = 0v ?v sns = 150mv out = 3v ?v sns = 300mv v cc (v) 0 i gnd (ma) ?7 ?4 ?3 ?6 ?5 ?2 ?1 0 4363 g21 ?80?70?60?50 ?20 ?40 ?10 ?30 v cc = shdn v cc (v) 0 ?v sns (mv) 60 50 40 30 55 45 35 4363 g22 80706050 20 40 10 30 out = 3v out = 0v
lt4363 8 4363fa pin functions enout: open collector enable output. the enout pin goes high impedance when the voltage at the out pin is within 0.5v of v cc and 3v above gnd, indicating the external mosfet is fully on. the state of the pin is latched until the out pin voltage drops below 2v, resetting the latch. the internal npn is capable of sinking up to 2ma of current. exposed pad (dfn package only): exposed pad may be left open or connected to device ground (gnd). fb: voltage regulator feedback input. connect this pin to the center tap of the resistive divider connected between the out pin and ground. during an overvoltage condition, the gate pin is controlled to maintain a 1.275v threshold at the fb pin. connect to gnd to disable the ov clamp. f lt : open collector fault output. this pin pulls low after the voltage at the tmr pin has reached the fault threshold of 1.275v. it indicates the pass transistor is about to turn off because either the supply voltage has stayed at an elevated level for an extended period of time (voltage fault) or the device is in an overcurrent condition (current fault). the internal npn is capable of sinking up to 2ma of current. gate: n-channel mosfet gate drive output. the gate pin is pulled up by an internal charge pump current source and clamped to 14v above the out pin. both voltage and cur - rent amplifiers control the gate pin to regulate the output voltage and limit the current through the mosfet. gnd: device ground. out: output voltage sense input. this pin senses the voltage at the source of the external n-channel mosfet. the voltage difference between v cc and out sets the fault timer current. when this difference drops below 0.5v, the en pin goes high impedance. ov (lt4363-2): overvoltage comparator input. when ov is above its threshold of 1.275v, the fault retry function is inhibited even when the tmr pin voltage has reached its retry threshold. as soon as the voltage at ov pin falls below its lower threshold the gate pin is allowed to turn back on. connect to gnd if unused. shdn: shutdown control input. the lt4363 can be shutdown to a low current mode by pulling the shdn pin below the threshold of 0.4v. pull this pin above 2.1v or disconnect it to allow the internal current source to turn the part back on. the leakage current to ground at the pin should be limited to no more than 1a if no external pull up is used to turn the part on. the shdn pin can be pulled up to 100v or below gnd by 60v without damage. sns: current sense input. connect this pin to the input of the current sense resistor. the current limit circuit controls the gate pin to limit the sense voltage between sns and out pins to 50mv. this is reduced to 25mv in a severe fault when out is below 2v. when in current limit mode, a current source charges up the tmr pin. the voltage difference with the out pin must be limited to less than 30v. connect to out pin if unused. tmr: fault timer input. connect a capacitor between this pin and ground to set the times for early fault warning, fault turn-off, and cool down periods. the current charg - ing up this pin during fault conditions depends on the voltage difference between the v cc and out pins. when tmr reaches 1.275v, the f lt pin pulls low to indicate the detection of a fault condition. if the condition persists, the pass transistor turns off when tmr reaches the threshold of 1.375v. a 2a current source then continues to pull the tmr up. when tmr reaches 4.3v, the 2a current reverses direction and starts to pull the tmr pin low. when tmr reaches the retry threshold of 0.5v, the gate pin pulls high turning back on the pass transistor for the lt4363-2 version. the gate pin latches low after fault time out for the lt4363-1. uv: undervoltage comparator input. when uv falls below its threshold of 1.275v, the gate is pulled down with a 1ma current. when uv rises above 1.275v plus the hys - teresis, the pull down current disappears and the gate pin is pulled up by the internal charge pump. if unused, connect to v cc . v cc : positive supply voltage input. the positive supply input ranges from 4v to 80v for normal operation. it can also be pulled below ground by up to 60v during a reverse battery condition, without damaging the part. shutting down the lt4363 by pulling the shdn pin to ground will reduce the supply current to 7a.
lt4363 9 4363fa block diagram + ? + ? sns v cc shdn ov (lt4363-2 only) ia 50mv/ 25mv 2a 1.375v 13v 1.275v 1.275v 4.3v 1.275v ? + 0.5v out tmr gnd gate uv 4363 bd v cc i tmr flt enout fb + ? charge pump control logic gateoff flt va shdn retry uv + ? ? + + ? ? + ? +
lt4363 10 4363fa operation some power systems must cope with high voltage surges of short duration such as those in vehicles. load circuitry must be protected from these transients, yet high availability systems must continue operating during these events. the lt4363 is an overvoltage protection regulator that drives an external n-channel mosfet as the pass transis - tor. it operates from a wide supply voltage range of 4v to 80v. it can also be pulled below ground potential by up to 60v without damage. the low power supply require - ment of 4v allows it to operate even during cold cranking conditions in automotive applications. the internal charge pump turns on the n-channel mosfet to supply current to the loads with very little power loss. two mosfets can be connected back to back to replace an inline schottky diode for reverse input protection. this improves the ef - ficiency and increases the available supply voltage level to the load circuitry during cold crank. normally, the pass transistor is fully on, powering the loads with very little voltage drop. when the supply voltage surges too high, the voltage amplifier (va) controls the gate of the mosfet and regulates the voltage at the out pin to a level that is set by the external resistive divider from the out pin to ground and the internal 1.275v reference. a current source starts charging up the capacitor connected at the tmr pin to ground. if the tmr voltage reaches 1.275v, the f lt pin pulls low to indicate impending turn-off due to the overvoltage condition. the pass transistor stays on until tmr reaches 1.375v, at which point the gate pin pulls low turning off the mosfet. a current continues to pull the tmr pin up until it reaches about 4.3v, at which point the current reverses direction and pulls the tmr pin down. for the lt4363-2 version, when the voltage at the tmr pin reaches 0.5v the gate pin begins rising, turning on the mosfet. the f lt pin will then return to a high impedance state. for the latch-off version, lt4363-1, both the gate and f lt pins remain low even after tmr has reached the 0.5v threshold. allow sufficient time for tmr to discharge to 0.5v and for the mosfet to cool before attempting to reset the part. to reset, pull the shdn pin low for at least 100s, then pull high with a slew rate of at least 10v/ms. the fault timer allows the load to continue functioning during short transient events while protecting the mosfet from being damaged by a long period of supply overvoltage, such as a load dump in vehicles. the timer period varies with the voltage across the mosfet. a higher voltage cor - responds to a shorter fault timer period, helping to keep the mosfet within its safe operating area (soa). the lt4363 senses an overcurrent condition by monitor - ing the voltage across an optional sense resistor placed between the sns and out pins. an active current limit circuit (ia) controls the gate pin to limit the sense volt - age to 50mv, if the out pin potential is above 2v. in the case of a severe output short that brings out below 2v, the servo sense voltage is reduced to 25mv to reduce the stress on the pass transistor. during current limit, the current charging the tmr capacitor is about 5 times the current during an overvoltage event. the f lt pin pulls low when the tmr voltage reaches 1.275v and the mosfet is turned off when it reaches 1.375v. the mosfet turns back on and the f lt pin returns to a high impedance state after tmr has reached the 0.5v threshold for the lt4363 - 2 version. for the latch-off version, lt4363-1, both the gate and f lt pins remain low even after tmr has reached the 0.5v threshold. reset the part in the same way as in overvoltage time-out case. an accurate undervoltage comparator keeps the gate pin low until the voltage at the uv pin is above the 1.275v threshold. an overvoltage comparator prevents the mosfet from turning on after fault time-out while the voltage at the ov pin is still above 1.275v for the lt4363 - 2. the shdn pin turns off the pass transistor and all the internal circuitry, reducing the supply current to a mere 7a.
lt4363 11 4363fa applications information the lt4363 limits the voltage and current delivered to the load during supply transient or output overload events. the total fault timer period is set to ride through short-duration faults, while longer events cause the output to shut off and protect the mosfet pass device from damage. the mosfet provides a low resistance path from the input to the load during normal operation, while in fault conditions it operates as a series regulator. overvoltage fault the lt4363 limits the voltage at the output during an overvoltage at the input. an internal amplifier regulates the gate pin to maintain 1.275v at the fb pin. during this interval the mosfet is on and supplies current to the load. this allows uninterrupted operation during short overvoltage events. if the overvoltage condition persists, the timer causes the mosfet to turn off. overcurrent fault the lt4363 features and adjustable current limit that pro - tects against output short circuits or excessive load current. during an overcurrent event, the gate pin is regulated to limit the current sense voltage across the sns and out pins to 50mv. in the case of a severe short at the output, where out is less than 2v, the current sense voltage is reduced to 25mv to further reduce power dissipation in the mosfet. if the overcurrent condition persists, the timer causes the mosfet to turn off. fault timer overview overvoltage and overcurrent conditions are limited in duration by an adjustable timer. a capacitor at the tmr pin sets the delay time before a fault condition is reported at the f lt pin as well as the overall delay before the mosfet is turned off. the same capacitor also sets the cool down time before the mosfet is allowed to turn back on. when either an overvoltage or overcurrent fault condition occurs, a current source charges the tmr pin capacitor. the exact current level varies as a function of the type of fault and the v ds voltage drop across the mosfet. this scheme takes better advantage of the mosfets available safe operating area (soa) than would a fixed timer current. the tmr pin is biased to 0.5v under normal operating conditions. in the presence of a fault the timer first charges to 1.275v, and then enters the early warning phase of operation. at this point the f lt pin pulls low and after charging to 1.375v, the timer shuts off the mosfet. the warning phase is indicated by f lt low and gives time for the load to perform house-keeping chores such as data storage in anticipation of impending power loss. after faulting off, the timer enters the cool down phase. at the end of the cool down period the lt4363-1 remains off until reset, while the lt4363-2 automatically restarts. for the lt4363-2 retry is inhibited if the ov pin is greater than 1.275v. this prevents motorboating in the event there is a sustained input overvoltage condition. fault timer operation in overvoltage in the presence of an overvoltage condition when the lt4363 regulates the output voltage, the timer charges from 0.5v to 1.275v with a current that varies as a func - tion of v ds (see figure 1). v ds is inferred from the drop across v cc and out. the timer current increases linearly from around 4a with v ds 0.5v, to 50a with v ds = 75v. because v ds is measured indirectly, clamping or filtering at the v cc pin affects the timer current response. a graph of overvoltage tmr current vs (v cc C v out ) is shown in the typical performance characteristics. when tmr reaches 1.275v, the f lt pin is latched low as an early warning of impending shutdown. the timer cur - rent is cut to a fixed value of 6a and continues to run until tmr reaches 1.375v, producing a fixed early warning period given by: c tmr = t warning ? 6a 100mv when tmr reaches 1.375v, the mosfet is turned off and allowed to cool for an extended period. the total elapsed time between the onset of output regulation and turn-off is given by: t reg = c tmr ? 0.775v i tmr + 100mv 6a ? ? ? ? ? ? because i tmr is a function of v cc C v out , the exact time in regulation depends upon the input waveform and the time required for the output voltage to come into regulation.
lt4363 12 4363fa t flt = 15.5ms/f total fault timer = t flt + t warning t warning = 16.67ms/f t flt = 96.9ms/f t warning = 16.67ms/f v tmr(v) i tmr = 6a i tmr = 6a v ds = 75v (i tmr = 50a) v ds = 10v (i tmr = 8a) 1.375 1.275 time 4363 f01 0.50 fault timer operation in overcurrent tmr pin behavior in overcurrent is substantially the same as in overvoltage. in the presence of an overcurrent con - dition when the lt4363 regulates the output current, the timer charges from 0.5v to 1.275v with a current that varies as a function of v ds (see figure 2). the current is about 5 times the value produced in overvoltage, under similar conditions v ds , increasing linearly from 8a with v ds < 0.5v to 260a with v ds = 80v. v ds is inferred from the drop across v cc and out. because v ds is measured indirectly, clamping or filtering at the v cc pin affects the timer current response. a graph of overcurrent tmr cur - rent vs (v cc C v out ) is shown in the typical performance characteristics. when tmr reaches 1.275v, the f lt pin is latched low as an early warning of impending shutdown. but unlike the overvoltage case, the timer current is not reduced and instead continues unabated until tmr reaches 1.375v, producing an early warning period given by: c tmr = t warning ? i tmr 100mv when tmr reaches 1.375v, the mosfet is turned off and allowed to cool for an extended period. the total elapsed time between the onset of current limiting and turn-off is given by: t lim = c tmr ? 0.875v i tmr because i tmr is a function of v cc C v out , the exact time in current limit depends upon the input waveform and the time required for the output current to come into regulation. cool down phase cool down behavior is the same whether initiated by overvoltage or overcurrent. during the cool down phase, the timer continues to charge from 1.375v to 4.3v with 2a, and then discharges back down to 0.5v with 2a, for a total equivalent voltage swing of 6.725v. the cool down time is given by: t cool = c tmr ? 2.925v + 3.8v 2a up to this point the operation of the lt4363-1 and lt4363-2 is the same. behavior at the end of the cool down phase and in response to the shdn pin is entirely different. at the end of the cool down phase the lt4363-1 remains latched off and f lt remains low. it may be restarted by pulling the shdn pin low for at least 100s or by cycling power. the cool down phase may be interrupted at any - time by pulling shdn low for at least 1s/f of c tmr ; the lt4363-1 will restart when shdn goes high. the lt4363-2 will automatically retry at the end of the cool down phase. retry is inhibited if the ov pin is above 1.275v; this prevents repetitive retries while the input is held in a sustained overvoltage condition. retry is auto - applications information figure 1. overvoltage fault timer current figure 2. overcurrent fault timer current t flt = 2.98ms/f total fault timer = t flt + t warning t flt = 22.14ms/f t warning = 2.86ms/f t warning = 0.38ms/f v tmr(v) v ds = 10v (i tmr = 35a) 1.375 1.275 0.50 time 4363 f02 v ds = 80v (i tmr = 260a)
lt4363 13 4363fa applications information matically initiated once the ov pin falls below 1.268v. ov has no effect on initial start-up when power is first applied and upon exiting shutdown. the cool down phase may be interrupted in the lt4363-2 by pulling shdn low for at least 1s/f of c tmr . for both the lt4363-1 and lt4363-2 the f lt pin goes high in shutdown and is cleared high when power is first applied to v cc . if f lt is set low, it can be reset during the cool down phase by pulling shdn low for at least 1s/f of c tmr . intermittent fault conditions brief overvoltage or overcurrent conditions interrupt the operation of the timer. if the tmr pin has not yet reached 1.275v when the input falls below the regulation value or drops out of current limit, the timer capacitor is dis - charged back to 0.5v with a 2a current sink. if the tmr voltage crosses 1.275v f lt is set low. if the overvoltage or overcurrent abates before reaching 1.375v, the timer capacitor discharges with 2a back to 0.5v, whereupon f lt resets high. if several short overvoltage or overcurrent events occur in rapid succession, the timer capacitor will integrate the charging and discharging currents. mosfet selection the lt4363 drives an n-channel mosfet to conduct the load current. the important features of the mosfet are on-resistance r ds(on) , the maximum drain-source voltage v (br)dss , the threshold voltage, and the soa. the maximum allowable drain-source voltage must be higher than the supply voltage. if the output is shorted to ground or during an overvoltage event, the full supply voltage will appear across the mosfet. the gate drive for the mosfet is guaranteed to be more than 10v and less than 16v for those applications with v cc higher than 9v. this allows the use of standard threshold voltage n-channel mosfets. for systems with v cc less than 9v, a logic level mosfet is required since the gate drive can be as low as 4.5v. the soa of the mosfet must encompass all fault condi - tions. in normal operation the pass transistor is fully on, dissipating very little power. but during either overvoltage or overcurrent faults, the gate pin is controlled to regu - late either the output voltage or the current through the mosfet. large current and high voltage drop across the mosfet can coexist in these cases. the soa curves of the mosfet must be considered carefully along with the selection of the fault timer capacitor. transient stress in the mosfet during an overvoltage event, the lt4363 drives a series pass mosfet to regulate the output voltage at an acceptable level. the load circuitry may continue operating throughout this interval, but only at the expense of dissipation in the mosfet pass device. mosfet dissipation or stress is a function of the input voltage waveform, regulation voltage and load current. the mosfet must be sized to survive this stress. most transient event specifications use the prototypi - cal waveshape shown in figure 3, comprising a linear ramp of rise time t r , reaching a peak voltage of v pk and exponentially decaying back to v in with a time constant of . a common automotive transient specification has constants of t r ?= 10s, v pk = 80v and = 1ms. a surge condition known as load dump commonly has constants of t r = 5ms, v pk = 60v and = 200ms. mosfet stress is the result of power dissipated within the device. for long duration surges of 100ms or more, stress is increasingly dominated by heat transfer; this is a matter of device packaging and mounting, and heat sink thermal mass. this is best analyzed by simulation, using the mosfet thermal model. for short duration transients of less than 100ms, mosfet survival is increasingly a matter of safe operating area figure 3. prototypical transient waveform v pk v in 4363 f03 t r
lt4363 14 4363fa (soa), an intrinsic property of the mosfet. soa quanti - fies the time required at any given condition of v ds and i d to raise the junction temperature of the mosfet to its rated maximum. mosfet soa is expressed in units of watt-squared-seconds (p 2 t). this figure is essentially con - stant for intervals of less than 100ms for any given device type, and rises to infinity under dc operating conditions. destruction mechanisms other than bulk die temperature distort the lines of an accurately drawn soa graph so that p 2 t is not the same for all combinations of i d and v ds . in particular p 2 t tends to degrade as v ds approaches the maximum rating, rendering some devices useless for absorbing energy above a certain voltage. when a fast input voltage step occurs, the current through the pass transistor to supply the load and charge up the out - put capacitor can be high enough to trigger an overcurrent event. the gate pulls low to 1v above the out pin, turning off the mosfet momentarily. the internal charge pump will then start to pull the gate pin high and turn on the mosfet to support the load current and charge up the out pin. the fault timer may not start yet because the current level is below the overcurrent limit threshold and the output voltage has not reached the servo voltage. this extra stress needs to be included in calculating the overall stress level of the mosfet. calculating transient stress to select a mosfet suitable for any given application, the soa stress must be calculated for each input transient which shall not interrupt operation. it is then a simple matter to choose a device which has adequate soa to survive the maximum calculated stress. p 2 t for a prototypical transient waveform is calculated as follows (figure 4): let a = v reg C v in b = v pk C v in (v in = nominal input voltage) then p 2 t = i load 2 ? 1 3 t r b ? a ( ) 3 b + 1 2 2a 2 ln b a + 3a 2 + b 2 ? 4ab ? ? ? ? ? ? ? ? ? ? ? ? ? ? typically v reg v in and ? t r simplifying the above to p 2 t = 1 2 i load 2 v pk ? v reg ( ) 2 [w 2 s] for the transient conditions of v pk = 80v, v in = 12v, v reg = 16v, t r = 10s and = 1ms, and a load current of 3a, p 2 t is 18.4w 2 s C easily handled by a mosfet in a dpak package. the p 2 t of other transient waveshapes is evaluated by integrating the square of mosfet power over time. ltspice can be used to simulate timer behavior for more complex transients and cases where overvoltage and overcurrent faults coexist. calculating short-circuit stress soa stress must also be calculated for short-circuit condi - tions. short-circuit p 2 t is given by: p 2 t = v ds ? v sns r sns ? ? ? ? ? ? 2 ? t tmr [w 2 s] where ? v ds is the voltage across the mosfet, and ? v sns is the sns pin threshold, and t tmr is the overcurrent timer interval. for v in = 15v, ? v ds = 13v (v out = 2v), ? v sns = 50mv, r sns = 12m and c tmr = 100nf, p 2 t is 6.3w 2 s C less than the transient soa calculated in the previous example. nevertheless, to account for circuit tolerances this figure should be doubled to 12.6w 2 s. applications information figure 4. safe operating area required to survive prototypical transient waveform v pk v in 4363 f04 v reg t r
lt4363 15 4363fa c tmr 0.1f r sns 10m q1 irlr2908 q2 irlr2908 v in 12v v out 12v, 3a clamped at 16v 4363 f06 lt4363de-2 gnd tmr 9 12 out 2 sns 3 shdn 6 uv 8 ov 7 v cc 5 flt enout fb 10 11 1 c1 47nf d1* smaj58ca r2 4.99k r1 57.6k gate 4 r7 10k r5 1m q3 2n3904 d2 1n4148 r3 10 r4 10 *diodes inc. applications information figure 6. overvoltage regulator with n-channel mosfet reverse input protection figure 5. external gate network limiting inrush current and gate pin compensation the lt4363 limits the inrush current to any load capacitance by controlling the gate pin voltage slew rate. an external capacitor can be connected from gate to ground to reduce the inrush current at the expense of slower turn-off time. the gate capacitor is set at: c1 = i gate(up) i inrush ? c l the lt4363 does not need extra compensation compo - nents at the gate pin for stability during an overvoltage or overcurrent event. with transient input voltage slew rates faster than 5v/s, a gate capacitor, c1, to ground is needed to prevent self enhancement of the n-channel mosfet. the extra gate capacitance slows down the turn off time during fault conditions and may allow excessive current during an output short event. an extra resistor, r1, in series with the gate capacitor can improve the turn off time. a diode, d1, should be placed across r1 with the cathode connected to c1 as shown in figure 5. threshold during a fault. the pass transistor is not allowed to turn back on even after the cool down period has finished. this prevents the pass transistor from cycling between on and off states when the input voltage stays at an elevated level for a long period of time, reducing the stress on the n-channel mosfet. for the latch-off version, lt4363-1, the overvoltage comparator function is not available. reverse input protection a blocking diode is commonly employed to protect the load when reverse input is possible, such as in automo - tive applications. this diode causes extra power loss, generates heat, and reduces the available supply voltage range. during cold crank, the extra voltage drop across the diode is particularly undesirable. the lt4363 is designed to withstand reverse voltage with - out damage to itself. the v cc , shdn , uv, and ov pins can withstand up to 60v of dc voltage below the gnd potential. back-to-back mosfets must be used to block the current path through q1s body diode (figure 6). figure 7 shows the approach with a p-channel mosfet in place of q2. c1 r3 4363 f05 lt4363 gate q1 r1 d1 in4148w undervoltage/overvoltage comparators the lt4363 has both undervoltage and overvoltage com - parators that can be used to sense the input supply volt - age. when the voltage at the uv pin is below the 1.275v threshold, the gate pin is held low to keep the external mosfet off. the supply voltage at the v cc pin should be at least 4v for the uv comparator to function. the overvoltage comparator prevents the lt4363-2 from restarting if the voltage at the ov pin is above the 1.275v
lt4363 16 4363fa applications information shutdown the lt4363 can be shut down to a low current mode when the voltage at the shdn pin is pulled below the shutdown threshold of 0.4v. the quiescent current drops down to 7a with internal circuitry turned off. the shdn pin can be pulled up to 100v or below gnd by up to 60v without damage. leaving the pin open allows an internal current source to pull it up and turn on the part while clamping the pin to 2.2v. the leakage current at the pin should be limited to no more than 1a if no pull up device is used to help turn it on. supply transient protection the lt4363 is tested to operate to 80v and guaranteed to be safe from damage up to 100v. nevertheless, voltage transients above 100v may cause permanent damage. during a short-circuit condition, the large change in cur - rent flowing through power supply traces and associated wiring can cause inductive voltage transients which could exceed 100v. to minimize the voltage transients, the power trace parasitic inductance should be minimized by using wide traces. a small rc filter, in figure 8, at the v cc pin will clamp the voltage spikes. another way to limit transients above 100v at the v cc pin is to use a zener diode and a resistor, d1 and r7 in figure 8. the zener diode limits the voltage at the pin while the resistor limits the current through the diode to a safe level during the surge. however, d1 can be omitted if the filtered voltage, due to r7 and c1, at the v cc pin is below 100v. the inclusion of r7 in series with the v cc pin will increase the minimum required voltage at v in due to the extra voltage drop across it. this voltage drop is due to the supply current of the lt4363 and the leakage current of d1. a total bulk capacitance of at least 22f low esr electro - lytic is required close to the source pin of mosfet q1. in addition, the bulk capacitance should be at least 10 times larger than the total ceramic bypassing capacitor on the input of the dc/dc converter. layout considerations to achieve accurate current sensing, kelvin connection to the current sense resistor (r sns in figure 8) is recom- mended. the minimum trace width for 1 oz copper foil is 0.02" per amp to ensure the trace stays at a reasonable temperature. 0.03" per amp or wider is recommended. note that 1oz copper exhibits a sheet resistance of about 530?/square. small resistances can cause large errors in figure 8. overvoltage regulator with input voltage detection c tmr 47nf r sns 10m q1 fdb33n25 v in v out 4363 f08 lt4363de-2 gnd tmr 9 12 out 2 sns 3 fb 1 c2 0.1f d1* smaj58a r2 4.99k r1 100k r7 1k gate 4 v cc 5 r3 10 *diodes inc. **sanyo 25ce22ga shdn 6 uv 8 ov 7 dc/dc converter gnd shdn v cc flt enout 10 11 c l ** 22f fault r5 90.9k r6 10k r4 374k c1 47nf c tmr 0.1f r sns 10m q1 irlr2908 q2 si7461dp v in 12v v out 12v, 3a clamped at 16v 4363 f07 lt4363de-2 gnd tmr 9 12 out 2 sns 3 v cc 5 fb 1 d1* smaj58ca r2 4.99k r1 57.6k gate 4 r7 10k d2 1n5245 15v r3 10 *diodes inc. shdn 6 uv 8 ov 7 flt enout 10 11 c1 47nf figure 7. overvoltage regulator with p-channel mosfet reverse input protection
lt4363 17 4363fa applications information high current applications. noise immunity will be improved significantly by locating resistive dividers close to the pins with short v cc and gnd traces. design example as a design example, take an application with the follow - ing specifications: v cc = 8v to 14v dc with a transient of 150v and decay time constant ( ) of 400ms, v out 27v, current limit (i lim ) at 5a, low battery detection of 6v, input overvoltage level at 60v, and 1ms of overvoltage early warning (figure 8). selection of smaj58a for d1 will limit the voltage at the v cc pin to less than 71v during 150v surge. the minimum required voltage at the v cc pin is 4v when v in is at 8v; the supply current for lt4363 is 1.5ma. the maximum value for r7 to ensure proper operation is: r7 = 8v ? 4v 1.5ma = 2.67k ? select 1k for r7 to accommodate all conditions. the maximum current through r7 into d1 is then calcu- lated as: i d1 = 150v ? 64v 1k ? = 86ma which is easily handled by the smaj58a for more than 500ms. with 0.1f of bypass capacitance, c1, along with 1k of r7, high voltage transients up to 200v with a pulse width less than 10s are filtered out at the v cc pin. next, calculate the resistive divider value to limit v out to 27v during an overvoltage event: v reg = 1.275v ? r1 + r2 ( ) r2 = 27v set the current through r1 and r2 during the overvoltage condition to 250a. r2 = 1.275v 250a = 5k ? choose 4.99k for r2. r1 = 27v ? 1.275v ( ) ? r2 1.275v = 100.7k ? the nearest standard value for r1 is 100k. next calculate the sense resistor, r sns , value: r sns = 50mv i lim = 50mv 5a = 10m ? c tmr is then chosen for 1ms of early warning time: c tmr = 1ms ? 6a 100mv = 60nf the nearest standard value for c tmr is 47nf. finally, calculate r4, r5, and r6 for 6v low battery detec - tion and 60v input overvoltage level: 6v ? r5 + r6 r4 + r5 + r6 = 1.275v 60v ? r6 r4 + r5 + r6 = 1.275v choose 10k for r6. r4 + r5 = 60v ? 10k ? 1.275v ? 10k ? = 460.6k ? r5 = 1.275v ? 460.6k ? + 10k ? 6v ? 10k ? = 90k ? r4 = 460.6k C 90k = 370.6k select 90.9k for r5 and 374k for r4. the pass transistor, q1, should be chosen to withstand a short-circuit with v cc = 14v. in the case of a severe output short where v out = 0v, the total overcurrent fault time is: t oc = 47nf ? 0.875v 45.5a = 0.904ms
lt4363 18 4363fa typical applications overvoltage regulator with output keep alive during shutdown c tmr 0.1f r sns 10m q1 irlr2908 v in v out 12v, 4a regulated at 16v 4363 ta02 lt4363de-2 gnd tmr 9 12 out 2 sns 3 fb 1 d1* smaj58a r2 24.9k r1 287k r7 1k gate 4 v cc 5 r3 10 r9 1k, 1w *diodes inc. **sanyo 25ce22ga shdn 6 uv 8 ov 7 flt enout 10 11 c l ** 22f r5 30.1k r6 10k r4 147k d2 1n4746a 18v 1w uv = 6v ov = 24v c1 47nf applications information the power dissipation in q1 is: p = 14v ? 25mv 10m ? = 35w during an output overload or soft short, the voltage at the out pin could stay at 2v or higher. the total overcurrent fault time when v out = 2v is: t oc = 47nf ? 0.875v 40a = 1.028ms the power dissipation in q1 is: p = 14v ? 2v ( ) ? 50mv 10m ? = 60w these conditions are well within the safe operating area of the fdb33n25.
lt4363 19 4363fa typical applications 2.5a, 48v hot swap with overvoltage output regulation at 72v c tmr 0.1f r sns 15m q1 fdb3632 v in v out 48v, 2.5a 4363 ta03 lt4363de-2 gnd tmr 9 12 out 2 sns 3 fb 1 d1* smat70a r2 4.02k r1 221k r7 1k gate 4 r3 10 shdn 6 uv *diodes inc. uv = 35v ov = 80v 8 v cc 5 ov 7 flt enout 10 11 c l 300f r5 13k r6 10k r4 604k c1 47nf 2.5a, 28v hot swap with overvoltage output regulation at 36v c tmr 0.1f r sns 15m q1 irlr2908 v in 28v v out 28v, 2.5a 4363 ta04 lt4363de-2 gnd tmr 9 12 out 2 sns 3 fb 1 d1* smaj58a r2 4.02k r1 110k r7 1k gate 4 r3 10 shdn 6 uv *diodes inc. uv = 18v ov = 36v 8 v cc 5 ov 7 flt enout 10 11 c l 300f r5 10k r6 10k r4 261k c1 47nf
lt4363 20 4363fa typical applications overvoltage regulator with reverse input protection up to C80v overvoltage regulator with 250v surge protection c tmr 0.1f r sns 10m q1 irlr2908 v in 12v v out 12v, 3a clamped at 16v 4363 ta05 lt4363de-2 gnd tmr 9 12 out 2 sns 3 fb 1 r2 4.99k r1 57.6k gate 4 v cc 5 r3 10 *diodes inc. **sanyo 25ce22ga ***optional component for reduced standby current shdn 6 uv 8 ov 7 flt enout 10 11 c l ** 22f q2 irlr2908 d1* smaj58ca r7 10k r5 1m q3 2n3904 d2 1n4148 d3** 1n4148 r4 10 c1 47nf 0.1f r3 10 r sns 10m q1 fdb33n25 q2 mps-a42 v in 12v 4363 ta07 lt4363de-2 gnd tmr out gate sns uv shdn ov fault output clamp at 16v enout flt fb d1* smaj58a *diodes inc. c l 22f c1 0.1f v cc dc/dc converter gnd shdn v cc r2 4.99k r4 127k r5 49.9k r1 57.6k c1 47nf r6 49.9k 9 12 23 1 4 5 6 8 7 10 11
lt4363 21 4363fa package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. de/ue package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695 rev d) 4.00 0.10 (2 sides) 3.00 0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.50 ref 1 6 12 7 pin 1 notch r = 0.20 or 0.35 45 chamfer pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (ue12/de12) dfn 0806 rev d 2.50 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 3.30 0.10 0.25 0.05 0.50 bsc 1.70 0.05 3.30 0.05 0.50 bsc 0.25 0.05
lt4363 22 4363fa .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0 ? 8 typ .008 ? .010 (0.203 ? 0.254) 1 n 2 3 4 5 6 7 8 n/2 .150 ? .157 (3.810 ? 3.988) note 3 16 15 14 13 .386 ? .394 (9.804 ? 10.008) note 3 .228 ? .244 (5.791 ? 6.197) 12 11 10 9 s16 0502 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc .245 min n 12 3 n/2 .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) s package 16-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) ms package 12-lead plastic msop (reference ltc dwg # 05-08-1668 rev ?) msop (ms12) 1107 rev ? 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 11 10 9 8 7 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
lt4363 23 4363fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 03/12 add 57.6k resistor to typical application 24
lt4363 24 4363fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2011 lt 0312 rev a ? printed in usa related parts typical application overvoltage regulator with ideal diode reverse voltage protection part number description comments ltc1696 overvoltage protection controller thinsot? package, 2.7v to 28v ltc2909 triple/dual inputs uv/ov negative monitor pin selectable input polarity allows negative and ov monitoring ltc2912/ltc2913 single/dual uv/ov voltage monitor ads uv and ov trip values, 1.5% threshold accuracy ltc2914 quad uv/ov monitor for positive and negative supplies ltc3827/ltc3827-1 low i q , dual, synchronous controller 4v v in 36v, 0.8v v out 10v, 80a quiescent current ltc3835/ltc3835-1 low i q , synchronous step-down controller single channel ltc3827/ltc3827-1 lt3845 low i q , synchronous step-down controller 4v v in 60v, 1.23v v out 36v, 120a quiescent current lt3850 dual, 550khz, 2-phase sychronous step-down controller dual 180 phased controllers, v in 4v to 24v, 97% duty cycle, 4mm w 4mm qfn-28, ssop-28 packages ltc3890 low i q , dual 2-phase, synchronous step-down controller 4v v in 60v, 0.8v v out 24v, 50a quiescent current LT4256 positive 48v hot swap controller with open-circuit detect foldback current limiting, open-circuit and overcurrent fault output, up to 80v supply ltc4260 positive high voltage hot swap controller with 8-bit adc and i 2 c wide operating range 8.5v to 80v lt4352 ideal mosfet oring diode external n-channel mosfets replace oring diodes, 0v to 18v ltc4354 negative voltage diode-or controller controls two n-channel mosfets, 1s turn-off, 80v operation ltc4355 positive voltage diode-or controller controls two n-channel mosfets, 0.5s turn-off, 80v operation lt4356 high voltage surge stopper 100v overvoltage and overcurrent protection, latch-off and auto-retry options ltc4365 window passer - ov, uv and reverse supply protection controller 2.5v to 34v operation, protects 60v to C40v 0.1f 10m irlr2908 output clamp at 16v 4363 ta06 lt4363 gnd tmr out sns fb 47nf 4.99k 57.6k gatev cc 10 ?60v to 75v dc protection 100v transient maximum uv = 4.5v shdn uv dc/dc converter gnd shdn v cc flt fault enout 22f 49.9k 127k ltc4357 gnd in out v dd gate m1 fdb3632 v in 12v d1 mmbd1205 d clamp smat70a

▲Up To Search▲

Price & Availability of LT4256

	To Download LT4256 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .